Methods of forming field effect transistors and field effect transistor circuitry

ABSTRACT

Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor&#39;s gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

TECHNICAL FIELD

[0001] This invention relates to methods of forming field effecttransistors, and to field effect transistor circuitry.

BACKGROUND OF THE INVENTION

[0002] It is desirable in transistors to be able to drive high currents.Driving high currents can enhance a transistor's operating performanceincluding its operating speed. In field effect transistors (FETs),current flow is primarily conducted by way of the drain-to-sourcecurrent I_(ds). While higher drive currents can be achieved by buildingwider FET devices, tradeoffs are made in valuable wafer real estate.Larger devices also typically have larger capacitances which canadversely impact device performance. Also typically, a high I_(ds)current in FET devices can result in an increased sub-threshold currentleakage. It is desirable in FETs to minimize the sub-threshold currentleakage. Accordingly, it is desirable to have the I_(ds) ratio ofon-state current (I_(on)) to off-state current (I_(off)) be as high aspossible. Such improves sub-threshold device leakage characteristics aswell as increases the transistor's operating speed performance.

[0003] This invention arose out of concerns associated with improvingfield effect transistor performance.

SUMMARY OF THE INVENTION

[0004] Methods of forming field effect transistors and resultant fieldeffect transistor circuitry are described. In one embodiment, asemiconductive substrate includes a field effect transistor having abody. A first resistive element is received by the substrate andconnected between the transistor's gate and the body. A second resistiveelement is received by the substrate and connected between the body anda reference voltage node. The first and second resistive elements form avoltage divider which is configured to selectively change thresholdvoltages of the field effect transistor with state changes in the gatevoltage. In a preferred embodiment, first and second diode assembliesare positioned over the substrate and connected between the gate andbody, and the body and a reference voltage node to provide the voltagedivider.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0006]FIG. 1 is a top plan view of a semiconductor wafer fragment inprocess in accordance with one embodiment of the invention.

[0007]FIG. 2 is a diagrammatic side sectional view of the FIG. 1 waferfragment taken along line 2-2 in FIG. 1.

[0008]FIG. 3 is a view of the FIG. 2 wafer fragment at a processing stepsubsequent to that shown in FIG. 2.

[0009]FIG. 4 is a top plan view of the FIG. 1 wafer fragment at aprocessing step subsequent to that shown in FIG. 1.

[0010]FIG. 5 is a view which is taken along line 5-5 in FIG. 4.

[0011]FIG. 6 is a view of the FIG. 5 wafer fragment at a processing stepsubsequent to that shown in FIG. 5.

[0012]FIG. 7 is a top plan view of the FIG. 4 wafer fragment at aprocessing step subsequent to that shown in FIG. 4.

[0013]FIG. 8 is a view of the FIG. 7 wafer fragment taken along line 8-8in FIG. 7.

[0014]FIG. 9 is a view of the FIG. 7 wafer fragment at a processing stepsubsequent to that shown in FIG. 7.

[0015]FIG. 10 is a view of the FIG. 9 wafer fragment taken along line10-10 in FIG. 9.

[0016]FIG. 11 is a view of the FIG. 9 wafer fragment at a processingstep which is subsequent to that shown in FIG. 9.

[0017]FIG. 12 is a view which is taken along line 12-12 in FIG. 11.

[0018]FIG. 13 is a view of the FIG. 11 wafer fragment at a processingstep subsequent to that shown in FIG. 11.

[0019]FIG. 14 is a view of the FIG. 13 wafer fragment at a processingstep subsequent to that shown in FIG. 13.

[0020]FIG. 15 is a view which is taken along line 15-15 in FIG. 14.

[0021]FIG. 16 is a view of the FIG. 14 wafer fragment at a processingstep subsequent to that shown in FIG. 14.

[0022]FIG. 17 is a schematic diagram of field effect transistorcircuitry constructed in accordance with a preferred embodiment of theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] This disclosure of the invention is submitted in furtherance ofthe constitutional purposes of the U.S. Patent Laws “to promote theprogress of science and useful arts” (Article 1, Section 8).

[0024] Referring to FIGS. 1 and 2, a semiconductor wafer fragment 20includes a semiconductive substrate 22 having a substrate region 23.Region 23 comprises a body of a field effect transistor which is to beformed. In the illustrated example, substrate 22 includes a buried megaeV (MeV) layer 24 and a pair of isolation regions 26 which collectivelyisolate the body. Where n-channel devices are to be formed, substrateregion 23 comprises p-type material and layer 24 comprises n-typematerial. Where p-channel devices are to be formed, substrate region 23comprises n-type material and layer 24 comprises p, type material. Layer24 and isolation regions 26 define an area 28 over or within which fieldeffect transistor circuitry is to be formed. The substrate can compriseany suitable substrate. In the context of this document, the term“semiconductive substrate” is defined to mean any constructioncomprising semiconductive material, including, but not limited to, bulksemiconductive materials such as a semiconductive wafer (either alone orin assemblies comprising other materials thereon), and semiconductivematerial layers (either alone or in assemblies comprising othermaterials). The term “substrate” refers to any supporting structure,including, but not limited to, the semiconductive substrates describedabove. The substrate can also comprise silicon-on-insulator substratesformed through various known techniques.

[0025] Referring to FIG. 3, a gate oxide layer 30 is formed oversubstrate 22.

[0026] Referring to FIGS. 4 and 5, a first patterned masking layer 32 isformed over substrate 22 and defines an opening 34 over area 28. Layer32 can comprise photoresist. Dopant is introduced into the substratethrough opening 34 to form a buried contact diffusion region 36. In theillustrated example, layer 24 comprises an n-type material, substrateregion 23 comprises a p-type material, and buried contact diffusionregion 36 comprises a p+ diffusion region. A wet oxide etch can beconducted either prior to or subsequent to formation of diffusion region36 to remove portions of oxide layer 30 from over the substrate areawhere dopant is to be introduced.

[0027] Referring to FIG. 6, first patterned masking layer 32 is removed.

[0028] Referring to FIGS. 7 and 8, a conductive material layer 38 isformed over substrate 22 and in electrical communication with buriedcontact diffusion region 36. In a preferred embodiment, layer 38 is inphysical contact with diffusion region 36. An exemplary material is insitu n-type doped polysilicon.

[0029] Referring to FIGS. 9 and 10, a patterned masking layer 40 isformed over substrate 22 and defines a conductive line pattern. Layer 40can comprise photoresist.

[0030] Referring to FIGS. 11 and 12, conductive layer 38 is etched toprovide a conductive line 42 which is in electrical communication withburied contact diffusion region 36 (FIG. 12). Conductive line 42includes a portion 44 which provides a gate for a field effecttransistor which is to be formed.

[0031] Referring to FIG. 13, a patterned masking layer 46 is formed oversubstrate 22 and includes masking openings 48, 50 and 52 over selectedportions of conductive line 42. Exposed conductive line portions arefirst doped with a first-type dopant which, in the preferred embodiment,comprises p-type dopant. In one embodiment, CMOS circuitry can becontemporaneously formed with the present field effect transistor. Inthis case, the p-type doping of the conductive line portions can alsodope other portions of the wafer where, for example, p-channel devicesare being formed. The p-type regions formed within conductive line 42are spaced-apart along and within the line. Layer 46 is subsequentlyremoved.

[0032] In this example, the material comprising conductive line 42 is insitu n-type doped polysilicon. Accordingly, the doping of the selectedportions of conductive line 42 just described provides alternatingregions of p-type dopant and n-type dopant within conductive line 42.Accordingly, a plurality of pn junctions 66 (FIG. 16) are distributedthroughout conductive line 42. In the event that the material comprisingconductive line 42 is not in situ doped n-type polysilicon, or in theevent conductive line 42 is desired to be rendered even more n-type, itcan be further doped with n-type impurity described just below.

[0033] Referring to FIG. 14, a patterned masking layer 54 is formed oversubstrate 22 and has masking openings over the illustrated cross-hatchedportions of conductive line 42 and other transistor structures whichdefine substrate areas within which source/drain regions are to beformed. Exposed conductive line portions are second doped with asecond-type dopant which is different from the first-type dopant.Preferably, the second-type dopant is n-type dopant. Doping also occurssufficiently to form source drain regions 62, 64 (FIG. 15) withinsubstrate 22. Desired spacing between diffusion regions 64 and 36, andthe dopant concentration of region 23 therebetween, can combine to avoidZener diode action.

[0034] The doping of the selected portions of conductive line 42 justdescribed provides alternating regions of p-type dopant and n-typedopant within conductive line 42. Accordingly, the dopings define aplurality of pn junctions 66 (FIG. 16) which are distributed throughoutconductive line 42.

[0035] In one embodiment, that portion of conductive line 42 comprisingthe gate line of the transistor can subjected to silicide processing. Inthis embodiment, spacers can be provided over the line, and a protectivelayer such as an oxide formed through decomposition of TEOS can beformed over the substrate and subsequently patterned to overlie regions72-80. The protective layer can also overlie other portions of thesubstrate which are not to be subjected to silicide processing. Arefractory metal such as titanium can be formed over the subjectpolysilicon, and subsequently heat processed to form a silicide layerover the substrate. The silicide can also be formed over thesource/drain regions depending upon design considerations.

[0036] Referring to FIG. 16, two nodes 68, 70 are provided. The nodesare provided by forming openings (designated at “x”) through aninsulative material (not shown), and subsequently filling the openingswith conductive material. Metal lines are provided over the insulativematerial and comprise node portions which are designated with the leadlines of designators 68, 70 respectively. Node 68 provides a referencevoltage node which extends to a reference voltage. Node 70 provides agate voltage node.

[0037] Referring to FIGS. 16 and 17, a plurality of regions 72, 74, 76,78 and 80 are formed within conductive line 42 and are arranged toprovide a voltage divider circuit which is connected between gate 44,body 23, and reference voltage node 68. The voltage divider circuit ispreferably configured to selectively change threshold voltages of thefield effect transistor with state changes in the gate voltage as willbecome apparent below.

[0038] In one embodiment, regions 72-80 are arranged to provide firstand second resistive elements received by, supported by, or preferablypositioned over the substrate and suitably connected to provide thevoltage divider circuit. In this example, a first resistive elementincludes regions 72, 74 and 76 (a first p-n-p structure), and a secondresistive element includes regions 76, 78 and 80 (a second p-n-pstructure).

[0039] In another embodiment, the plurality of regions 72-80 arearranged within conductive line 42 to provide first and second diodeassemblies 82, 84 (FIG. 17). The diode assemblies are received by,supported by, or preferably positioned over the substrate, with thefirst diode assembly 82 connected between gate 44 and body 23, andsecond diode assembly 84 connected between body 23 and reference voltagenode 68.

[0040] In a preferred embodiment, first diode assembly 82 comprises apair of diodes D₁, D₂. Each diode has an anode and a cathode, with thecathodes being connected together in a cathode-connected configurationas shown. The anode of diode D ₁ is connected with gate 44 while theanode of diode D₂ is connected with body 23. Diode assembly 84preferably comprises a pair of diodes D₃, D₄, each diode having an anodeand a cathode with the cathodes being connected together in acathode-connected configuration as shown. The anode of diode D₃ isconnected to body 23, and the anode of D₄ is connected to referencevoltage node 68.

[0041] In operation, the field effect transistor of the presentinvention provides monolithic transistor construction with a bi-levelthreshold voltage which increases the ratio of I_(on) to I_(off.) Thetransistor's gate is operably connected with the substrate and isconfigured to change the potential of the substrate. Accordingly, thetransistor is selectively configurable by the substrate potential tohave different threshold voltages. As an example, with the drain currentbeing in the pico ampere range, when the gate voltage V_(G) is high(e.g. 3.3 volts), the bulk or body is at 0 volts and the thresholdvoltage is adjusted by the enhancement implant to be between 0.5 voltsto 0 volts. This is desirable for an aggressive I_(DS) conduction. Whenthe gate voltage V_(G) is low (e.g. 0 volts), the bulk or body is at−1.5 volts and the threshold voltage moves up to 1.0 volts according tothe doping profile in the bulk of the n-channel device. In this example,the reference voltage V_(ref) is −3.0 volts. The gate voltage can beless than 0 volts depending on the gate-induced drain leakage of thedevice as well.

[0042] Field-effect transistors constructed in accordance with theinvention can have enhanced speed performance which justifies anyincrease in circuit layout. Other advantages of the invention caninclude a fairly simplified process flow which enhances themanufacturability of the device. The field effect transistor can haveimproved drive, as well as an improved on/off current ratio.Accordingly, faster devices can be implemented in current CMOStechnologies without sacrificing subthreshold and/or stand-by current.

[0043] While the inventive methods and structures have been described inthe context of n-channel devices, it is to be understood that theinventive methods and structures can be equally well-suited forapplication with p-channel devices, with consideration being given forthe inherent differences between n- and p-channel devices.

[0044] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described. since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. Field effect transistor circuitry comprising: a semiconductivesubstrate; and a field effect transistor supported by the substrate andhaving a gate operably connected with the substrate and configured tochange substrate potentials, the transistor being selectivelyconfigurable by the substrate potential to have different thresholdvoltages.
 2. Field effect transistor circuitry comprising: asemiconductive substrate; a field effect transistor supported by thesubstrate and having a gate, the transistor further having a bodyreceived by the substrate and isolated therewithin, the transistor beingselectively configurable by the gate to have different thresholdvoltages.
 3. Field effect transistor circuitry comprising: asemiconductive substrate; a field effect transistor supported by thesubstrate and having a body, the transistor having a gate; a firstresistive element positioned over the substrate and connected betweenthe gate and the body; and a second resistive element positioned overthe substrate and connected between the body and a reference voltagenode.
 4. Field effect transistor circuitry comprising: a semiconductivesubstrate; a field effect transistor supported by the substrate andhaving a body, the transistor having a gate; a first resistive elementsupported by the substrate and connected between the gate and the body;and a second resistive element supported by the substrate and connectedbetween the body and a reference voltage node, the first and secondresistive elements forming a voltage divider configured to selectivelychange threshold voltages of the field effect transistor with statechanges in the gate voltage.
 5. The field effect transistor circuitry ofclaim 4, wherein the first and second resistive elements are positionedover the substrate.
 6. The field effect transistor circuitry of claim 4,wherein the first resistive element comprises a pn junction.
 7. Thefield effect transistor circuitry of claim 4, wherein the firstresistive element comprises two pn junctions.
 8. The field effecttransistor circuitry of claim 4, wherein the second resistive elementcomprises a pn junction.
 9. The field effect transistor circuitry ofclaim 4, wherein the second resistive element comprises two pnjunctions.
 10. The field effect transistor circuitry of claim 4, whereinboth the first and second resistive elements comprise a pair of pnjunctions.
 11. The field effect transistor circuitry of claim 4, whereinthe gate comprises a conductive line which extends to the voltagereference node, and at least one of the first and second resistiveelements is disposed within the conductive line intermediate the gateand the voltage reference node.
 12. The field effect transistorcircuitry of claim 11, wherein: both of the resistive elements aredisposed within the conductive line; and the first and second resistiveelements collectively comprise a plurality of pn junctions.
 13. Fieldeffect transistor circuitry comprising: a semiconductive substrate; afield effect transistor supported by the substrate and having a bodywithin the substrate, the transistor having a gate; a first diodeassembly supported by the substrate and connected between the gate andthe body; and a second diode assembly supported by the substrate andconnected between the body a reference voltage node.
 14. Field effecttransistor circuitry comprising: a semiconductive substrate; a fieldeffect transistor supported by the substrate and having a body withinthe substrate, the transistor having a gate; a first diode assemblysupported by the substrate and connected between the gate and the body;and a second diode assembly supported by the substrate and connectedbetween the body a reference voltage node, the first and second diodeassemblies forming a voltage divider configured to selectively changethreshold voltages of the field effect transistor with state changes inthe gate voltage.
 15. The field effect transistor circuitry of claim 14,wherein the first and second diode assemblies are positioned over thesubstrate.
 16. The field effect transistor circuitry of claim 14,wherein the gate comprises a conductive line which extends to thereference voltage node, and wherein the first and second diodeassemblies are received by the conductive line.
 17. The field effecttransistor circuitry of claim 14, wherein: the first diode assemblycomprises a pair of diodes, each diode having an anode and a cathode,the cathodes being connected together; and the second diode assemblycomprises a pair of diodes, each diode having an anode and a cathode,the cathodes being connected together.
 18. The field effect transistorcircuitry of claim 17, wherein: the anode of one diode of the firstdiode assembly is connected to the gate; the anode of the other diode ofthe first diode assembly is connected to the body; the anode of onediode of the second diode assembly is connected to the body; and theanode of the other diode of the second diode assembly is connected tothe reference voltage node.
 19. The field effect transistor circuitry ofclaim 14, wherein: the gate comprises a conductive line which extends tothe reference voltage node, and wherein the first and second diodeassemblies are received by the conductive line; the first diode assemblycomprises a pair of diodes, each diode having an anode and a cathode,the cathodes being connected together; and the second diode assemblycomprises a pair of diodes, each diode having an anode and a cathode,the cathodes being connected together.
 20. The field effect transistorcircuitry of claim 14, wherein: the gate comprises a conductive linewhich extends to the reference voltage node, and wherein the first andsecond diode assemblies are received by the conductive line; a the firstdiode assembly comprises a pair of diodes, each diode having an anodeand a cathode, the cathodes being connected together, the anode of onediode of the first diode assembly being connected to the gate, the anodeof the other diode of the first diode assembly being connected to thebody; and the second diode assembly comprises a pair of diodes, eachdiode having an anode and a cathode, the cathodes being connectedtogether, the anode of one diode of the second diode assembly beingconnected to the body, the anode of the other diode of the second diodeassembly being connected to the reference voltage node.
 21. Monolithicfield effect transistor circuitry comprising: a semiconductivesubstrate; a field effect transistor operably connected with thesubstrate and having a body therewith, the transistor having a gate; anda voltage divider circuit connected between the gate, the body, and areference voltage node, the circuit being configured to selectivelychange threshold voltages of the field effect transistor with statechanges in the gate voltage.
 22. The monolithic field effect transistorcircuitry of claim 21, wherein the voltage divider comprises a pair ofresistive elements.
 23. The monolithic field effect transistor circuitryof claim 21, wherein the voltage divider comprises a pair of diodeassemblies.
 24. The monolithic field effect transistor circuitry ofclaim 21, wherein: the gate comprises a conductive line which extends tothe reference voltage node; and the voltage divider comprises aplurality of p-type and n-type regions disposed within the conductiveline.
 25. The monolithic field effect transistor circuitry of claim 24,wherein plurality of p-type and n-type regions are arranged within theconductive line to provide first and second diode assemblies.
 26. Amethod of forming a field effect transistor comprising: providing asemiconductive substrate; forming a field effect transistor having abody within the substrate, the transistor having a gate; forming avoltage divider circuit over the substrate and connected with the gate,the body, and a reference voltage node, the circuit being configured toselectively change threshold voltages of the field effect transistorwhen the gate voltage changes from high to low, and vice versa.
 27. Themethod of forming a field effect transistor of claim 26, wherein theforming of the voltage divider circuit comprises: forming a conductivelayer of material over the substrate; etching the conductive layer ofmaterial to provide a conductive line, at least a portion of theconductive line providing the gate for the transistor, the conductiveline extending to the voltage reference node; and doping selectedportions of the conductive line to form first and second resistiveelements.
 28. The method of forming a field effect transistor of claim26, wherein the forming of the voltage divider circuit comprises:forming a conductive layer of material over the substrate; etching theconductive layer of material to provide a conductive line, at least aportion of the conductive line providing the gate for the transistor,the conductive line extending to the voltage reference node; firstdoping a first-type of dopant into the conductive line; and seconddoping a second-type of dopant into the conductive line, the first andsecond dopings providing a plurality p-type and n-type regions withinthe conductive line.
 29. The method of forming a field effect transistorof claim 26, wherein the forming of the voltage divider circuitcomprises: forming a conductive layer of material over the substrate;etching the conductive layer of material to provide a conductive line,at least a portion of the conductive line providing the gate for thetransistor, the conductive line extending to the voltage reference node;first doping a first-type of dopant into the conductive line; and seconddoping a second-type of dopant into the conductive line, the first andsecond dopings providing a plurality of pn junctions distributed alongthe line.
 30. The method of forming a field effect transistor of claim26, wherein the forming of the voltage divider circuit comprises:forming a conductive layer of material over the substrate; etching theconductive layer of material to provide a conductive line, at least aportion of the conductive line providing the gate for the transistor,the conductive line extending to the voltage reference node; firstdoping a first-type of dopant into the conductive line; and seconddoping a second-type of dopant into the conductive line, the first andsecond dopings providing a plurality of pn junctions distributed alongthe line, wherein two pn junctions are arranged to define a first pairof diodes, and two other pn junctions are arranged to define a secondpair of diodes.
 31. The method of forming a field effect transistor ofclaim 30, wherein the first pair of diodes are arranged in acathode-connected configuration, and the second pair of diodes arearranged in a cathode, connected configuration.
 32. A method of forminga field effect transistor comprising: providing a semiconductivesubstrate; forming a conductive layer of material over the substrate;patterning the conductive layer of material into a conductive line aportion of which comprises a gate for a field effect transistor; anddoping other portions of the conductive line sufficiently to form firstand second resistive elements, the resistive elements being operablyconnected with the gate and substrate and forming a voltage dividerconfigured to selectively manipulate threshold voltages of the fieldeffect transistor with changes in gate voltage.
 33. The method offorming a field effect transistor of claim 32 further comprising priorto the forming of the conductive layer, forming a buried contactdiffusion region within the substrate, wherein the patterning of theconductive layer comprises patterning said layer into a conductive lineover and in electrical communication with the buried contact diffusionregion.
 34. The method of forming a field effect transistor of claim 32,wherein the doping of the other portions of the conductive linecomprises forming the first resistive element to comprise a first p-n-pstructure, and forming the second resistive element to comprise a secondp-n-p structure.
 35. The method of forming a field effect transistor ofclaim 32, wherein the doping of the other portions of the conductiveline comprise providing alternating regions of p-type dopant and n-typedopant within the conductive line.
 36. The method of forming a fieldeffect transistor of claim 32, wherein the doping of the other portionsof the conductive line comprises first doping p-type dopant into theconductive line, and second doping n-type dopant into the conductiveline.
 37. A method of forming a field effect transistor comprising:forming a conductive line over a semiconductive substrate, a portion ofthe line forming a gate for a field effect transistor, another portionof the line electrically connecting with the substrate; doping theconductive line with a first-type dopant; doping the conductive linewith a second-type dopant which is different from the first-type dopant,the dopings defining, a plurality of pn junctions distributed throughoutthe conductive line between the gate and a reference node.
 38. Themethod of forming a field effect transistor of claim 37, wherein thedoping of the conductive line with the first-type dopant comprisesforming spaced-apart regions comprising the first-type dopant along andwithin the conductive line.
 39. The method of forming a field effecttransistor of claim 37, wherein the doping of the conductive line withthe second-type dopant comprises forming spaced-apart regions comprisingthe second-type dopant within the conductive line.
 40. The method offorming a field effect transistor of claim 37, wherein the first-typedopant comprises p-type dopant and the second-type dopant comprisesn-type dopant.
 41. The method of forming a field effect transistor ofclaim 37 further comprising prior to forming the conductive line,forming a buried contact diffusion region received within the substrate,the conductive line being formed to be in electrical communication withthe buried contact diffusion region.
 42. The method of forming a fieldeffect transistor of claim 37, wherein: the dopings define a pluralityof pn junctions arranged to provide first and second diode assemblies,the first diode assembly comprising a pair of cathode-connected diodes,the second diode assembly comprising a pair of cathode-connected diodes,the first and second diode assemblies being operably connected in avoltage divider configuration across the substrate to selectivelymanipulate the threshold voltage of the transistor with changes in thegate voltage.
 43. A method of forming integrated circuitry comprising:providing a semiconductive substrate; forming a first patterned maskinglayer over the substrate; doping into the substrate through the firstpatterned masking layer to form a buried contact; removing the firstpatterned masking layer; forming a conductive layer of material over thesubstrate and in electrical communication with the buried contact;patterning the conductive layer into a conductive line in electricalcommunication with the buried contact, a portion of the conductive lineproviding a field effect transistor gate; forming another patternedmasking layer over the substrate and having masking openings overselected portions of the conductive line; first doping into the selectedportions of the conductive line with a first-type dopant; removing theanother patterned masking layer; forming a different patterned maskinglayer over the substrate and having openings over different selectedportions of the conductive line; and second doping into the differentselected portions of the conductive line with a second-type dopant whichis different from the first-type dopant, the first and second dopingsdefining a plurality of pn junctions distributed throughout theconductive line between the gate and a reference node.